Semiconductor amplifiers are produced in many electrical circuits as so-called Darlington circuits comprising two transistors mutually connected in series. In the international patent application No. WO 85/04285, such amplifier devices are shown which have a bipolar transistor and an FET side by side on a common substructure. The transistors are mutually connected via a metal layer on the substructure surface. This device has the disadvantage that it is complicated to produce and requires a large area for the common substructure. There is also shown a Darlington circuit where the bipolar transistor is divided into a plurality of segments, each of which is surrounded by segments of the FET. The mutual substructure is thus utilised effectively and the device takes up a small amount of room, but has the disadvantage that it is relatively complicated to produce.
In the production of FET's, so-called complementary methods can be utilised, as are described in a conference report IEEE 1986 International Electron Devices Meeting Technical Digest, Los Angeles 7-10 Dec., pp 244-247, L. C. Parillo et al: "A Versatile High-Performance, Double-Level-Poly Double-Level. Metal, 1.2 Micron CMOS Technology". Two FET's are produced on a common substructure, one in a positively doped and the other in a negatively doped area. The method has the advantage that the two transistors can be manufactured using a relatively small number of procedural steps. However, the transistors shown are not connected in a Darlington circuit and it is not apparent, in the use of this method, whether the FET's can be connected to a still further component on the substructure.